Integrated circuits, particularly those implementing dynamic random access memory cells, often include storage capacitors. The capacitors are often coupled to regions of the semiconductor substrate to provide an electrical connection between the capacitor and other circuit elements. In forming this connection, it is desirable to minimize the resistance between the capacitor and the substrate.
Such capacitors may be formed within cavities or trenches in a dielectric layer disposed outwardly from a semiconductor substrate. During fabrication, the dielectric layer may be subject to elevated temperatures causing moisture and/or contaminants to diffuse from the sidewalls of the cavities. These impurities tend to oxidize the bottom of the cavity on the substrate where the capacitor will ultimately interface with the substrate. This layer of oxide contaminants increases the resistance of the interface.
One approach to removing oxide contaminants from the capacitor/substrate interface to reduce the resistance of this interface is to introduce a substance such as silane to the interface. Silane reduces the oxide, and thus acts to clean the interface. A problem with this approach is that it is generally ineffective in removing more than a monolayer of oxide. Another approach to removing contaminants is to remove impurities from the interface as they are created by performing a high vacuum prebake. In this approach, the interface is subject to a high temperature, such as 850 degrees Celsius, for a period of approximately 60 minutes. A high vacuum removes the contaminants as they volatilize during the prebake. A problem with this approach is that typical thermal budgets of many devices, such as dynamic random access memory cells, cannot withstand the duration of high temperature associated with this approach.